Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance

ABSTRACT

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority, under 35 U.S.C. §119(e), ofProvisional Application No. 62/053,540, filed Sep. 22, 2014,incorporated herein by this reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

BACKGROUND OF THE INVENTION

This invention is in the field of integrated circuit manufacture.Embodiments of this invention are more specifically directed to theformation of capacitors in memory devices such as ferroelectricmemories.

A recently developed technology for realizing non-volatile solid-statememory devices involves the construction of capacitors in which thedielectric material is a polarizable ferroelectric material, such aslead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT),rather than silicon dioxide or silicon nitride as typically used innon-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V)characteristic of the ferroelectric material, based on its polarizationstate, enables the non-volatile storage of binary states in thosecapacitors. In contrast, conventional MOS capacitors lose their storedcharge on power-down of the device.

Non-volatile solid-state read/write random access memory (RAM) devicesbased on ferroelectric capacitors, such memory devices commonly referredto as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, have beenimplemented in many electronic systems, particularly portable electronicdevices and systems. FRAMs are especially attractive in implantablemedical devices, such as pacemakers and defibrillators. Various memorycell architectures including ferroelectric capacitors are known in theart, including the well-known 1T1C (one transistor, two transistor) and2T2C (two transistor, two capacitor) cells, among others. Ferroelectriccapacitors are also implemented in some integrated circuits asprogrammable analog capacitors.

FIG. 1 a illustrates the construction of an example of a portion of anintegrated circuit including conventional 1T1C ferroelectric randomaccess memory (FRAM) cell 6. In this example, cell 6 includesferroelectric capacitor 2 and metal-oxide-semiconductor (MOS) transistor5, where one plate of capacitor 2 is connected to one end of thesource/drain path of transistor 5. Capacitor 2 and transistor 5 are bothdisposed at or near a semiconducting surface of a semiconductorsubstrate; alternatively, capacitor 2 and transistor 5 may instead beformed at the surface of a semiconductor layer that overlies aninsulator layer, such as according to a silicon-on-insulator (SOI)technology as known in the art. N-channel MOS transistor 5 in theexample of FIG. 1 a includes n-type source/drain regions 14 at thesurface of p-type substrate 10 (or of a p-type “well” formed intosubstrate 10, as the case may be), with gate electrode 16 overlying achannel region between source/drain regions 14, and separated from thatchannel region by gate dielectric 17, as conventional. Isolationdielectric structures 15 are disposed at or near the surface ofsubstrate 10 to isolate transistors from one another, in theconventional manner for MOS integrated circuits. Interlevel dielectric13 is disposed over transistor 5, with conductive plug 18 disposed in acontact opening through interlevel dielectric 13 to provide a conductiveconnection between one of source/drain regions 14 of transistor 5 andlower plate 20 a of ferroelectric capacitor 2. Gate electrode 16corresponds to the word line of cell 6, while the one of source/drainregions 14 not in contact with conductive plug 18 corresponds to the bitline of the column in which cell 6 resides.

In the example of FIG. 1 a, ferroelectric capacitor 2 is formed of aferroelectric “sandwich” stack of conductive plates 20 a, 20 b, betweenwhich ferroelectric material 22 is disposed. Lower conductive plate 20 ais formed at a location overlying conductive plug 18, so as to be inelectrical contact with the underlying source/drain region 14 oftransistor 5 by way of that conductive plug 18; upper conductive plate20 b will receive a plate line voltage during operation of cell 6, aswill be described below. Lower conductive plate 20 a and upper plate 20b are formed from one or more layers of conductive metals, metal oxides,and the like. A typical construction of lower conductive plate 20 a is astack of a diffusion barrier layer in contact with conductive plug 18and a layer of a noble metal (e.g., Ru, Pt, Ir, Rh, Pt, Pd, Au) or metaloxide (e.g., RuOx, IrOx, PdOx, SrRuO₃) overlying the barrier layer andin contact with the ferroelectric material 22. Conductive plates 20 a,20 b are typically formed of the same conductive material or materialsas one another, for purposes of symmetry, simplicity of themanufacturing flow, and improved ferroelectric polarization performance.As mentioned above, ferroelectric material 22 in capacitor 2 istypically lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate(SBT), either of which may be deposited by way of metalorganic chemicalvapor deposition. Ferroelectric material 22 is desirably as thin aspracticable, for purposes of electrical performance (e.g.,polarization), and for consistency with the deep sub-micron featuresused to realize modern integrated circuits.

FIG. 1 b illustrates an example of a Q-V characteristic of aconventional ferroelectric capacitor such as capacitor 2 of FIG. 1 a. Asshown, the charge (Q) stored across the conductive plates depends onboth the voltage currently applied to the plates (V) and the recenthistory of that voltage. In this example, capacitor 2 is polarized intothe “+1” state by application of a voltage V exceeding a “coercive”voltage +V_(α) across the capacitor plates (conductive plates 20 a, 20b). Once polarized to the “+1” state, capacitor 2 will exhibit a storedcharge of +Q₁ so long as voltage V remains above coercive voltage−V_(β). Conversely, if the voltage V applied across the capacitor platesis more negative than coercive voltage −V_(β), capacitor 2 is polarizedinto the “−1” state, and will exhibit a stored charge of −Q₂ for anapplied voltage V below +V_(α).

An important characteristic of ferroelectric capacitors, for purposes ofnon-volatile storage in integrated circuits, is the difference incapacitances exhibited by a ferroelectric capacitor in its respectivepolarized states. As fundamental in the art, capacitance is the ratio ofstored charge to applied voltage. Ferroelectric capacitors exhibit botha linear capacitance by virtue of its parallel plate construction, andalso a significant polarization capacitance by virtue of its response tochanges in polarization state upon application of a polarizing voltage.For example, referring to FIG. 1 b, the polarization of a ferroelectriccapacitor from its “−1” state to its “+1” state by an applied voltageabove coercive voltage V_(α) is reflected by a relatively highcapacitance C(−1) corresponding to the polarization charge stored in thecapacitor due to its change of polarization state. The differentialcharge stored as a result of the polarization of the capacitor from onestate to the opposite state is commonly referred to as the “switchingpolarization”. On the other hand, a capacitor that already in its “+1”state exhibits little capacitance C(+1) from re-polarization to the “+1”state, because its ferroelectric domains are already aligned in thedirection of the applied coercive voltage and thus little additionalpolarization charge is stored. Accordingly, the polarization state of aferroelectric memory cell (i.e., the stored data state) isconventionally read by application of a coercive voltage to theferroelectric capacitor and sensing the exhibited capacitance.

FIGS. 1 c and 1 d illustrate a read operation of an instance of FRAMcell 6 _(jk), which resides in column j and row k of an FRAM memoryarray. In this conventional approach, a read is performed by applying alow voltage V_(ss) to bit line BL_(k), then isolating bit line BL_(k) toleave it floating, and then raising the voltage of plate line PL fromthe low voltage V_(ss) to a high voltage V_(cc) above the coercivevoltage +V_(α) of capacitor 2 while word line WL_(j) is energized toturn on transistor 5. The high plate line voltage interrogates thepolarization capacitance of capacitor 2 according to the hysteresisdiagram of FIG. 1 a, producing a read current i_(R) through transistor 5to bit line BL_(k). Sense amplifier 8, coupled to bit line BL_(k),senses the voltage V_(BL) established at the (typically parasitic)capacitance BLC of bit line BL_(k) by read current i_(R) to discern thestored data state. As shown in FIG. 1 d, if capacitor 2 of cell 6 _(jk)was previously in the “+1” polarization state, the relatively low readcurrent i_(R) will establish a relatively low level (<V_(REF)) voltagetransition V(0) that will be interpreted by sense amplifier 8 as a “0”data state. Conversely, if capacitor 2 of cell 6 _(jk) was previously inthe “−1” polarization state, the stronger read current i_(R) willestablish a relatively high level (>V_(REF)) voltage transition V(1)that will be interpreted by sense amplifier 8 as a “1” data state. The“read margin” of cell 6 _(jk) corresponds to the difference in thelevels of read current i_(R), and the corresponding difference in bitline voltage V_(BL) relative to reference voltage V_(REF), establishedby the two polarization states of capacitor 2 in cell 6 _(jk).

As known in the art, ferroelectric capacitors and thus memoriesincorporating such devices are vulnerable over time to weakening of theswitching polarization, commonly referred to as “aging”. This weakeningcorresponds to collapse of the polarization hysteresis loop, for exampleas shown by curves 3+, 3− of FIG. 1 b. In the memory context, thisweakened switching polarization will appear as a loss of read margin anda corresponding increased likelihood of read errors.

It has been observed that exposure of ferroelectric integrated circuitsto high temperatures such as those encountered in manufacturingprocesses following the deposition of the ferroelectric material, willdegrade the polarization characteristics of that material. Examples ofsuch high temperature processes include those involved in forming metalconductor levels in the integrated circuit itself, packaging of theintegrated circuit (e.g., thermal curing of plastic mold compound),assembling the packaged device into its system application (e.g., solderreflow), and also operating the device at elevated temperatures.Extended or repeated exposure to temperature will degrade the ability ofthe material to fully repolarize, typically due to hydrogen diffusinginto the ferroelectric material. Accordingly, it is useful to minimizeexposure of the integrated circuit to high temperatures subsequent toferroelectric deposition.

By way of further background, packaging of the integrated circuit canalso result in mechanical stresses applied to the surface of the die,with such stresses being sufficient in some cases as to cause crackingof the protective overcoat film at the die or even displacement of metalconductors or other features so as to cause device failure. Thesestresses can be especially severe in the case of packages of the type inwhich a cured plastic mold compound encapsulates the integrated circuitdie. Various approaches for reducing the mechanical stresses caused bypackaging are known in the art. One approach is the application of astress relief layer, such as an organic film or coating, to the surfaceof the integrated circuit die prior to molding. The use of a polyimidefilm as this stress relief layer is widespread in the art, due to itscompatibility with photolithographic patterning and etching to exposethe bond pads of the die and its other favorable thermal and mechanicalproperties. According to conventional processing techniques, theformation of the polyimide film involves a final bake process to curethe material. This final bake is typically performed at an elevatedtemperature for a significant duration, for example at 375° C. for onehour. However, as discussed above, thermal processes following thefabrication of ferroelectric elements, such as ferroelectric capacitors,tend to degrade the switching polarization characteristics of thematerial and thus such performance parameters as read margin in FRAMapplications. As such, the conventional bake used to cure the polyimidestress relief film tends to degrade the ferroelectric material. Use ofthe polyimide stress relief film as applied in the conventional manneris thus discouraged for ferroelectric integrated circuits.

By way of further background, the packaging of integrated circuits intodie-size packages referred to in the art as wafer-chip-scale packages(“WCSP”), has become popular in the art. According to this approach, forexample as described in U.S. Patent Application Publication No. US2012/0211884 A1, published Aug. 23, 2012, commonly assigned herewith andincorporated herein by this reference, the WCSP eliminates encapsulationof the integrated circuit die with mold compound or the like, insteadforming solder balls or “bumps” onto conductive pads at the surface ofthe integrated circuit. Passivation layers, typically formed of apolyimide, are formed over the integrated circuit to define thelocations of the conductive pads, and in some cases to also insulate anadditional patterned conductive layer (i.e., a redistribution layer, or“RDL”) that routes signals from the solder balls to the bond pads of theintegrated circuit die. A WCSP is mounted to a printed circuit board byplacing it upside-down, with the solder balls at corresponding lands onthe circuit board; a solder reflow will then attach the package to theprinted circuit board via the reflowed solder balls.

As discussed above, the conventional polyimide cure processes involvedin WCSP technology will degrade the switching polarizationcharacteristics of ferroelectric material, especially if multiplepassivation layers are necessary because an RDL is required. Thisdegradation in polarization, and in read margin in the FRAM context, canbe sufficiently severe that the device cannot tolerate the additionaldegradation that will occur from the subsequent solder reflow process.Accordingly, WCSP technology has not been available for integratedcircuits, such as FRAMs, that include ferroelectric structures.

By way of further background, U.S. Pat. No. 8,778,774, which isincorporated herein by this reference, describes the application ofexternal mechanical stress to a semiconductor wafer to increase thepolarization of ferroelectric devices in integrated circuits on thatwafer.

BRIEF SUMMARY OF THE INVENTION

Disclosed embodiments provide a method of fabricating a ferroelectricintegrated circuit and the integrated circuit so fabricated in which thepolarization characteristics of the ferroelectric material are enhanced.

Disclosed embodiments provide such a method and integrated circuit thatcan tolerate subsequent thermal processes.

Disclosed embodiments provide such a method and integrated circuit thatprovides improved read margin for ferroelectric memories.

Disclosed embodiments provide such a method and integrated circuit inwhich the polarization characteristics are enhanced without requiringmodification of processes involved in forming the ferroelectricstructure.

Disclosed embodiments provide such a method and integrated circuit thatcan be packaged by way of wafer-chip-scale package (WCSP) technology.

Other objects and advantages of the disclosed embodiments will beapparent to those of ordinary skill in the art having reference to thefollowing specification together with its drawings.

According to certain embodiments, a passivation material is applied tothe surface of a ferroelectric integrated circuit die, and is cured to atensile stress state that imparts compressive stress to the underlyingferroelectric material. In one embodiment, the passivation material is apolyimide film that is cured by a thermal process with fast temperatureramp that heats the film to a temperature below the Curie temperature ofthe ferroelectric material for a short time period.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 a is a cross-sectional view illustrating a portion of anintegrated circuit including a ferroelectric capacitor constructedaccording to conventional methods.

FIG. 1 b is a plot of a charge-vs.-voltage characteristic of aconventional ferroelectric capacitor.

FIG. 1 c is an electrical diagrams, in schematic and block form,illustrating a conventional 1T-1C ferroelectric memory cell.

FIG. 1 d is a timing diagram illustrating the operation of a read of the1T-1C ferroelectric memory cell of FIG. 1 c.

FIG. 2 is a flow diagram illustrating the process flow for manufacturinga ferroelectric integrated circuit according to an embodiment.

FIG. 3 is a cross-sectional view, in schematic form, of a portion of anintegrated circuit fabricated according to the embodiment of FIG. 2, andillustrating the effect of an overlying passivation film on aferroelectric structure.

FIG. 4 is a cross-sectional view, in schematic form, of a portion of anintegrated circuit fabricated according to the embodiment of FIG. 2 aspackaged in a wafer-chip-scale package.

DETAILED DESCRIPTION OF THE INVENTION

The one or more embodiments described in this specification areimplemented into integrated circuits with ferroelectric memories such asferroelectric random access memories (FRAMs), as it is contemplated thatsuch implementation is particularly advantageous in that context.However, it is also contemplated that concepts of this invention may bebeneficially applied to in other applications, for example integratedcircuits with other types of ferroelectric structures and devices.Accordingly, it is to be understood that the following description isprovided by way of example only, and is not intended to limit the truescope of this invention as claimed.

It is known in the art that cured polyimide adheres well to the surfaceof an integrated circuit, and that such adhesion is important in theability of the polyimide film to serve as a stress relief agent for theintegrated circuit when packaged, for example in a molded plasticpackage. As mentioned above in connection with the Background of theInvention, however, the application of a stress relief film of polyimideor other materials that require curing or anneal is strongly discouragedfor integrated circuits that include ferroelectric devices, because thetime and temperature required for curing the stress relief filmsignificantly degrade the polarization characteristics of theferroelectric material. For a specific example, the typical curingprocess for a polyimide stress relief film is a bake at 375° C. for onthe order of one hour, which is essentially fatal to the polarizationcharacteristics of lead-zirconium-titanate (PZT) ferroelectric material.It is believed that this degradation results from the diffusion ofhydrogen into the ferroelectric film, such diffusion accelerated by thetime and temperature required to cure polyimide in the conventionalmanner. Accordingly, conventional ferroelectric devices are typicallypackaged without use of a polyimide stress relief film. This inabilityto use polyimide with ferroelectric integrated circuits essentiallyrenders impossible the use of wafer-chip-scale package (WCSP) technologyfor ferroelectric devices, as one or more polyimide passivation filmsare necessary to form the solder balls and redistribution conductorlayers in such packages.

However, it has been observed, in connection with this invention, thatpolyimide film, when cured, exhibits an intrinsic tensile stress. It hasbeen further observed, also in connection with this invention, thatbecause of the excellent adhesion of cured polyimide to the surface ofan integrated circuit, the intrinsic tensile stress in the curedpolyimide film exerts a compressive stress on thin film layers in theunderlying integrated circuit to such an extent that the polarizationcharacteristics of the ferroelectric material are enhanced. According tothis invention, an approach has been discovered for curing a passivationfilm, such as polyimide, at the surface of a ferroelectric integratedcircuit such that the intrinsic tensile stress in the cured passivationfilm imparts beneficial compressive stress in underlying ferroelectricmaterial, without degrading the polarization of that ferroelectricmaterial due to hydrogen diffusion or other time-and-temperaturepolarization degradation mechanisms. Embodiments incorporating thisdiscovery will now be described in detail.

FIG. 2 illustrates a process flow, according to certain embodiments, forfabricating an integrated circuit with ferroelectric circuit elements,such as ferroelectric capacitors in the form described above relative toFIGS. 1 a through 1 d, such that the polarization characteristics of theferroelectric material are enhanced. This process flow begins withprocess 30, in which transistors such as transistor 5 of FIG. 1 a areformed at or near the semiconducting surface of a substrate or othersupport body in the conventional manner. In particular, it iscontemplated that the substrate may correspond to single-crystal siliconwith the appropriate dopant concentration, along with such structures asisolation dielectric structures and the appropriate doped wells asdesired; alternatively, in the silicon-on-insulator context, it iscontemplated that the substrate may correspond to a “handle” wafer onwhich an insulating layer is formed, with the transistors and othercircuit elements formed in an overlying epitaxial silicon layer. Ineither case, such structures and features as a gate dielectric layer,gate electrodes, source/drain regions, and the like, are formed at ornear the surface of the substrate according to conventional MOSprocesses. In the CMOS context, these transistors may include bothp-channel MOS and n-channel MOS transistors. Other circuit elements suchas MOS capacitors, resistors, and the like may also be fabricated inthis process 30, with interlevel dielectric layers formed and contactopenings formed through such layers as appropriate for the particularcircuit layout.

Following process 30 in the process flow of FIG. 2, a ferroelectriccapacitor such as capacitor 2 of FIG. 1 a is then formed, beginning withprocess 32 in which one or more conductive layers are formed to serve asthe lower conductive plate layer. Typically, process 32 will beperformed by sputter deposition of one or more layers of the desiredconductive material, such as one or more of strontium ruthenate(SrRuO₃), iridium (Ir), iridium oxide (IrO₂), platinum (Pt), and othermetals and metal oxides suitable for use in this application, along withthe appropriate barrier metal layers disposed between the lowerconductive plate layer and underlying structures, as conventional in theart. In many implementations, the particular conductors deposited inprocess 32 are selected for compatibility with the ferroelectricmaterial to be deposited over this layer, and with the temperatures andother conditions that the structure will be exposed to in the remainderof the manufacturing process. Following the deposition of the lowerconductive plate layer in process 32, ferroelectric material such aslead-zirconium-titanate (PZT) is deposited overall by way ofmetalorganic chemical vapor deposition, in process 34. Examples ofdeposition processes suitable for use in process 34 according to thisembodiment are described in U.S. Pat. No. 6,730,354, and No. 8,962,350,both commonly assigned herewith and incorporated herein by reference.Upon completion of PZT deposition process 34, an upper conductive platelayer is then deposited over the ferroelectric material in process 36,for example by way of sputter deposition. It is contemplated that thecomposition of this upper conductive plate layer will typically be thesame as that of lower conductive plate layer, for symmetry and to allowthe use of the same materials and processes for each. If lower and upperconductive plate layers are composed of a stack of multiple conductivematerials, the order of deposition of those materials in the upper platelayer will typically be reversed from that for the lower plate layer. Inprocess 38, the ferroelectric capacitor is then completed byphotolithographic patterning of photoresist or another mask layer todefine its size and location, followed by a single masked stack etch ofthe upper and lower conductive plate layers and the ferroelectricmaterial between those layers. Commonly assigned U.S. Pat. No.6,656,748, incorporated herein by reference, describes an example offerroelectric stack formation and etch that is suitable for use asprocess 38 in connection with embodiments of this invention. Also inprocess 38, a ferroelectric passivation film may optionally be formedover the etched capacitor structure, such as described in U.S. PatentPublication No. 2013/0056811, published Mar. 7, 2013, commonly assignedherewith and incorporated herein by this reference.

In process 40, conventional processes for forming one or more levels ofmetal conductors are then performed to define interconnections among thevarious circuit elements in the integrated circuit being formed. Astypical in the art, process 40 for a given level of interconnection willinclude the deposition of a interlevel dielectric layer, a patternedetch of that interlevel dielectric layer to form vias and contacts tounderlying conductors, deposition of conductive material including atleast a layer of a metal conductor and perhaps conductive plugs to fillvias through the interlevel dielectric, and a patterned etch of themetal layer to define the routing of the metal conductors in that level.Process 40 is repeated as desired to form additional conductor levels;integrated circuits with six or seven metal levels are common in theart.

The particular material of the metal layer or layers deposited andpatterned in process 40 may be aluminum, copper, other conventionalmetals, or alloys and other combinations of these metals, as known inthe art. As known in the art, copper metallization typically requiresthe use of an underlying barrier layer, typically silicon nitride, tolimit the diffusion of copper into the underlying transistors. However,also as known in the art, silicon nitride tends to contain a relativelyhigh concentration of hydrogen, which may diffuse into and thus degradethe ferroelectric material as a result of subsequent thermal processes.Aluminum metallization typically contains less hydrogen, and is thusbelieved to be more compatible with ferroelectric integrated circuits.But as will become apparent from this description, the describedembodiments enable the use of copper metallization even with a siliconnitride barrier layer, while avoiding degradation in the polarizationcharacteristics of the ferroelectric material.

Following process 40, a protective overcoat layer, typically composed ofsilicon nitride or silicon oxynitride, is deposited overall in process42. In process 44, photolithographic patterning and etching of theprotective overcoat is then performed to form openings over the bondpads in the upper metal level, in the conventional manner.

According to this embodiment, a passivation film is then deposited overthe surface of the integrated circuit in process 46. The composition ofthis passivation film is of a material that attains a stress state whencured in the manner to be described below according to this embodiment,such that the stress state of the cured passivation film exerts a stresson the underlying ferroelectric circuit elements in the integratedcircuit. An example of such a passivation film is a polyimide, such asthe HD4100 polyimide product available from HD MicroSystems. Othermaterials suitable for use as the passivation film includepolybenzoxazole (PBO), benzocyclobutene-based polymers (BCB),fluoro-polymers, and other polymer-containing soft stress releasematerials having a low elastic modulus as compared with SiO₂. Process 46may be performed in the conventional manner for the selected passivationfilm material, for example by spinning on or otherwise dispensing thepassivation film material onto the surface of the wafer, to a thicknesson the order of several micrometers. An example of a passivation filmdispensed in process 44 according to this embodiment is a 10 μm layer ofthe HD4100 polyimide.

In process 47, selected locations of the passivation film deposited inprocess 44 is photolithographically removed, for example to expose thebond pads previously exposed by the etch of the underlying protectiveovercoat in process 42. If the passivation film is a photosensitivepolyimide or similar film, the bond pad openings and other selectedlocations of the film will be removed in process 47 by masked exposureand developing of the film as appropriate for the particular material.If the passivation film requires chemical etching, process 47 willinvolve conventional photolithographic pattern and etch processes.According to this alternative, it is contemplated that the previousprotective overcoat etch of process 42 may in some cases be omitted fromthe process flow, with process 47 then including both an etch of thepassivation film and an etch of the underlying protective overcoat toexpose the bond pads in the upper metal level.

Process 48 is then performed to cure the passivation film deposited inprocess 44. In a general sense, cure process 48 is performed by heatingthe wafer including the integrated circuit being fabricated, with thepassivation film deposited in process 44, to a selected cure temperaturefor a selected time duration at that cure temperature. According tothese embodiments, the time and temperature conditions of cure process48 are selected so as to cure the passivation film into a state in whichit exhibits an intrinsic tensile stress sufficient to impart acompressive stress in underlying ferroelectric material, withoutdegrading the polarization of that ferroelectric material due tohydrogen diffusion or other time-and-temperature polarizationdegradation mechanisms. It is contemplated that the range of conditionsof cure process 48 will depend, at least in part, on the specificmaterials used for the ferroelectric material and the passivation film.

However, certain general limits for the time and temperature conditionsof cure process 48 have been discovered in connection with theseembodiments. As known in the art, ferroelectric material exhibits a“Curie temperature”, which is defined as the temperature at which,absent an externally applied electric field, the crystal structure ofthe ferroelectric material undergoes a phase change that causes loss ofpolarization. While the depolarized material will repolarize onapplication of a coercive voltage, it is believed that repeated orextended exposure of the ferroelectric material to temperatures abovethe Curie temperature will result in some permanent degradation in itspolarization characteristics. As such, cure process 48 in thisembodiment is carried out at a cure temperature below the Curietemperature of the ferroelectric material deposited in process 34. Thiscure temperature is contemplated to be the temperature measured at thewafer, for example by way of a non-contact IR pyrometer.

Secondly, as noted above, the duration of high temperature exposure ofthe ferroelectric material is a significant factor in the degradation ofits polarization characteristics. Accordingly, cure process 48 in thisembodiment is performed by minimizing the time at which the curetemperature is maintained, and by maximizing the ramp rate at which thewafer is heated to the cure temperature and then cooled from the curetemperature, so as to minimize the overall exposure of the ferroelectricmaterial to high temperatures in cure process 48.

An example of cure process 48 that has been observed, by experiment, toenhance the polarization characteristics of PZT ferroelectric material,is carried out by way of electromagnetic heating. In this embodiment,the electromagnetic heating of process 48 involves the application ofelectromagnetic energy to the passivation film at a frequency thatcouples to the vibrational frequency of the polymer of the passivationfilm, which heats and cures the film. One type of electromagneticheating that has been observed to be suitable for cure process 48 ismicrowave heating, such as may be applied by a variable frequencymicrowave system in which the frequency of the electromagnetic wave canbe selected (e.g., over a range from about 5 GHz to about 9 GHz) so asto efficiently couple to the polymer of the particular passivation film.As known in the art (for example as described in U.S. Pat. No.7,939,456, incorporated herein by reference), variable frequencymicrowave heating is typically performed by selecting a center frequencyfor the microwave energy, and then rapidly and substantiallycontinuously sweeping the frequency over a frequency range about thatcenter frequency, for example over a range of ±5% about the centerfrequency, although this range may vary based on the particularequipment used. In this example of cure process 48, the wafer or wafersincluding integrated circuits with ferroelectric circuit elementsfabricated as described above, including a passivation film of HD4100polyimide at a thickness of about 10 μm, are placed into the vacuumchamber of a variable frequency microwave system and heated by theapplication of microwave energy at a center frequency of about 6.25 GHz,modulated over a range of about ±6.25%_(0.4 GHz). This variablefrequency microwave energy heats the wafer to a cure temperature,measured at the wafer, of at least about 340° C. and at or below about390° C. (400° C. being the Curie temperature of the deposited PZT inthis example), for example at about 360° C., for less than twentyminutes, for example for about five to ten minutes.

The use of electromagnetic heating to carry out cure process 48 iscontemplated to be especially beneficial in connection with theseembodiments, considering that the electromagnetic energy can couple tothe organic molecules of the polyimide passivation film (and similarlyto other organic materials as used for the passivation film) much morestrongly than it can to the inorganic molecules of the underlyingintegrated circuit, including the ferroelectric material. Accordingly,this difference in coupling efficiently heats the passivation film tocarry out the curing mechanism, while minimizing the energy delivered tothe ferroelectric material. As such, the use of electromagnetic heatingoperates to control the thermal exposure of the device in cure process48, but does not directly impact the performance of the ferroelectricmaterial. In fact, it is contemplated that the only heating of theferroelectric material caused by electromagnetic curing used in process48 will be heat conducted from the passivation film to the ferroelectricmaterial through the intervening layers therebetween. Accordingly, it iscontemplated that the electromagnetic heating of the passivation film iswell-suited to curing that film in the minimum time, so as to minimizetemperature exposure of the underlying ferroelectric material.

Variable frequency microwave is believed to be a particularly usefultype of electromagnetic heating for use in curing process 48. As knownin the art, for example as described in the above-incorporated U.S. Pat.No. 7,939,456, variable frequency microwave heating in the processing ofsemiconductor wafers avoids damaging arc formation, and also providesmore uniform heating over the wafer. This more uniform heating providedby variable frequency microwave energy is believed to significantlyimprove the curing of the passivation film in process 48 in thisembodiment, enabling shorter cure times and thus reducing thedegradation of the underlying ferroelectric material by exposure to theelevated curing temperature.

The heating of the wafer from ambient temperature to the curetemperature, as measured by a non-contact IR pyrometer directed at thewafer surface (i.e., the polyimide passivation film) to the curetemperature is carried out in this example at a ramp rate of at least0.40° C. per second, for example at 0.60° C. per second. The ramp rateat which the wafer returns to the ambient temperature from the curetemperature should also be maximized, in this embodiment, with adesirable ramp rate being at least 0.40° C. per second, for example at0.60° C. per second. It is contemplated that heating and cooling ramprates resembling a “step function” would be desirable, to the extentattainable in physical systems, considering that the extent of thecuring mechanism from the temperatures below the eventual curetemperature are expected to be insignificant while the degrading effectson the ferroelectric material of the temperature exposure in those rampperiods will be cumulative. In this regard, it is contemplated that useof a smaller capacity variable frequency microwave system, such as asingle-wafer system, in curing process 48 may further reduce degradationof the ferroelectric material, as such smaller systems will tend to haveshorter cool-down times than larger batch systems.

It is contemplated that other approaches to curing the passivation filmin process 48 may alternatively be used. For example, it is contemplatedthat rapid thermal anneal (RTA) may be a suitable technology for cureprocess 48. In this regard, it is contemplated that relatively simplemodifications to the configuration of conventional RTA systems willenable their use in cure process 48 according to these embodiments.

Other approaches to cure process 48 that limit the time at the curetemperature while sufficiently curing the passivation film are alsocontemplated.

FIG. 3 schematically illustrates the result of passivation filmdeposition process 44 and cure process 48 on the underlyingferroelectric structures. In this example, ferroelectric capacitor 55has been formed at or near the surface of substrate 52, and includeslower and upper plates 60 a, 60 b on either side of ferroelectricmaterial 62. Dielectric material 54 is disposed over and around lowerand upper plates 60 a, 60 b and ferroelectric material 62, and includesthe various interlevel dielectric layers that insulate the metal levels(not shown) in the integrated circuit, as well as the protectiveovercoat layer deposited in process 42. In this schematic view of FIG.3, polyimide passivation film 60 is disposed over dielectric material54.

As evident by the force arrows shown in FIG. 3, upon curing of polyimidepassivation film 60 in cure process 48 according to these embodiments,passivation film 60 exhibits an intrinsic tensile stress. Because of theexcellent adhesion of polyimide passivation film 60 to the surface ofdielectric material 54, as is typical in conventional integratedcircuits, this tensile stress state of passivation film 60 imparts acompressive stress on the underlying dielectric material 54. Thiscompressive stress on dielectric material 54 will be transferred also toferroelectric material 62, as evident by the force arrow shown in FIG. 3for that layer. This compressive stress has been observed to improve thepolarization performance of ferroelectric material 62.

Referring back to FIG. 2, programming process 45 may optionally beperformed prior to cure process 48. For example, as shown in FIG. 2,programming process 47 is performed after access to the bond pads orother terminals of the integrated circuit is provided by way of thepatterned etch of the protective overcoat in process 46, prior todeposition of the passivation film. It has been observed, in connectionwith some embodiments, that the enhancement in the polarizationcharacteristics of ferroelectric circuit elements resulting from thecompressive stress imparted to the ferroelectric material by the curedpassivation film, as discussed above relative to FIG. 3, is furtherenhanced in those cases in which the ferroelectric material isprogrammed (i.e., polarized) prior to cure process 48. Accordingly,programming process 47 is performed by the application of a voltage toeach of the ferroelectric structures in the integrated circuit that isat or above the coercive voltage for those ferroelectric structures.Typically, it is contemplated that this programming process 47 will beperformed using conventional automated test equipment, for example atthe time that the wafer containing the integrated circuits iselectrically tested following its fabrication (e.g., at any time afterprotective overcoat process 42 and prior to cure process 48).

It has also been observed, in connection with some of these embodiments,that the polarity of the polarization applied in programming process 47can affect the enhancement effect of the applied compressive stress onthe ferroelectric material. For the example of ferroelectric capacitorsthat are electrically arranged similarly as the ferroelectric memorycell described above relative to FIGS. 1 a through 1 c, it has beenobserved that the polarization enhancement is increased by programmingprocess 47 programming a “0” data state on the ferroelectric capacitor,as compared with process 47 programming a “1” data state. Morespecifically, in the arrangement of FIGS. 2 a through 1 d in which apositive plate line voltage is applied to upper conductive plate 20 b ofFIG. 1 a, the “0” data state (i.e., the state exhibiting the V(0)transition in FIG. 1 d) corresponds to the “+1” polarization state inthe hysteresis diagram of FIG. 1 b. In general, this preferredpolarization state programmed in process 47 is that for which theferroelectric material is not polarized to the opposite state by theapplication of the read voltage.

While a preferred polarization state (e.g., the “0” data state) forprogramming process 47 may be exhibited by the ferroelectric structures,the less preferred polarization state (in this example, the “1” datastate) may still exhibit some additional enhancement as compared withthat resulting from cure process 48 for unpolarized (or “native”)ferroelectric material. However, as noted above, significant enhancementin the polarization characteristics of the ferroelectric material isstill attained even without the additional benefit of thepre-polarization of the ferroelectric material. As such, programmingprocess 47 is optional according to this embodiment.

Following cure process 48, assembly and test process 50 is thenperformed on the integrated circuits in the conventional manner. Asknown in the art, assembly/test process 50 includes such assemblyoperations as the dicing of integrated circuits from wafer form,mounting of the individual dies to a lead frame or other package, wirebonding or other bonding to electrically connect the bond pads of theintegrated circuit to leads of the eventual package, and completion ofthe package by molding (and curing) plastic mold compound around thelead frame and die or otherwise sealing the package, depending on theparticular plastic or ceramic packaging technology being used.Electrical test of the packaged integrated circuit is then alsoperformed as part of assembly/test process 50, including the exercise ofthe ferroelectric structures in those integrated circuits as appropriatefor the desired device functionality. Assembly/test process 50 may alsoinclude the mounting of the packaged integrated circuit to a printedcircuit board or other system implementation, such as by way of solderreflow or wave soldering, whether performed by the manufacturer of theintegrated circuit or by a customer or other end user.

According to some embodiments, as mentioned above, these embodimentsenable the packaging of ferroelectric integrated circuits in packages ofthe type referred to in the art as wafer-chip-scale packages (WCSP).These packages are essentially at the size of the die itself, and relyon solder balls that are separated from the integrated circuit surfaceby polyimide or other passivation layers. And as mentioned above, thedegradation of polarization characteristics resulting from conventionalcure processes for these passivation layers has effectively precludedthe use of WCSP technology for ferroelectric devices. However, theenhanced polarization performance, and the resulting improved readmargin for FRAM devices in particular, as provided by the passivationcure processes implemented according to these embodiments, has enabledthe use of WCSP technology for FRAMs and other ferroelectric devices.

FIG. 4 illustrates, in cross-section, a ferroelectric integrated circuitpackaged in a WCSP package according to an embodiment. In this example,integrated circuit die 70 has its circuit components 72 formed at andnear the semiconducting surface of its substrate, as described above inconnection with the process flow of FIG. 2. As suggested generally inFIG. 4, these circuit components 72 include ferroelectric capacitors 55.Conductive pad 74 corresponds to a bond pad at the surface of die 70,and is electrically coupled with the active circuitry 72. Firstpassivation layer 76 is a layer of a polyimide or other suitablepassivation material that has been dispensed onto the surface of die 70,and patterned to expose a portion of pad 74 as shown. According to thisembodiment, cure process 48 cures passivation layer 76 by heating thestructure to a cure temperature below the Curie temperature of theferroelectric material in capacitors 55, for a duration sufficient forpassivation layer 76 to attain a tensile stress state but not so long asto significantly degrade the polarization characteristics of theferroelectric material, as described above.

Redistribution layer (RDL) 78 is a conductive layer deposited andpatterned at the surface of first passivation layer to electricallycouple with pad 74. RDL layer 78 as patterned extends over the surfaceof first passivation layer 76 from pad 74 to a location at whichexternal electrical contact is to be formed. In this example, secondpassivation layer 80, which is also of a polyimide or other suitablepassivation material, is dispensed onto the surface of first passivationlayer 76 and RDL layer 80, cured by way of cure process 48, andpatterned to expose RDL 18 at a selected location. It is contemplatedthat the stress exerted by second passivation layer 80 onto theferroelectric material of capacitors 55 will be attenuated consideringthat it is in indirect contact only with the surface of die 70 (i.e.,via first passivation layer 76). As such, the duration of the secondinstance of cure process 48 performed for second passivation layer 80need only be of such a duration as to attain structural integrity.Alternatively, it is contemplated that passivation layers 76, 80 mayboth be dispensed and patterned prior to cure, such that a singleinstance of cure process 48 may be performed to place both layers into atensile stress state that imparts compressive stress to theferroelectric material of capacitors 55, without degrading thepolarization characteristics of that material as described above.

The WCSP package of FIG. 3 is completed by the deposition and patterningof a conductive metal layer to form under bump metallization (“UBM”) pad82 at the location of the opening through second passivation layer 80 atwhich RDL 78 is exposed. Solder ball 84 is then formed at UBM pad 82, inthe conventional manner. As known in the art, UBM layer 82 protects theexposed edges of second passivation layer 80 from delamination of secondpassivation layer 80 from the underlying RDL 78, which would provide apath for contamination and, in some situations, short circuits amongelements of RDL 78. UBM 82 can also serve as a diffusion barrier to thematerial of solder ball 84.

Alternatively, as known in the art, if solder ball 84 can be formed overpad 74 at the surface of die 70, only a single passivation layer 76 (andsingle instance of cure process 48) would be necessary.

In any event, the dispensing and curing of passivation layers such aspolyimide in the WCSP context, as described above relative to FIG. 4according to these embodiments, can enhance rather than degrade thepolarization characteristics of ferroelectric material in circuitelements of the packaged integrated circuit die. As known in the art,most if not all ferroelectric dielectric materials also exhibit apiezoelectric effect such that the ferroelectric characteristics of thematerial can be altered by applied stresses. It is contemplated thatsome combination of the stress applied by the cured passivation layer,the heat of the curing process, and the electric field within theferroelectric capacitor permanently and physically reorients domains inthe ferroelectric material in parallel with that electric field, andthat this realignment of the domains enhances the polarizationcharacteristics of the ferroelectric material, increasing the signalmargin of the device. In addition, because the curing of thesepassivation layers according to these embodiments is carried out in away that does not significantly degrade the polarization characteristicsof the ferroelectric material, the ferroelectric material is better ableto tolerate the temperature exposure involved in the solder reflowinvolved in the mounting of the WCSP package to a printed circuit board.Indeed, it is believed that these embodiments enable ferroelectricintegrated circuits to be packaged as WCSPs, which was not previouslypracticable due to the polarization degradation caused by theconventional polyimide cure and solder reflow processes.

It is therefore contemplated that the enhancement of the polarizationcharacteristics of ferroelectric materials provided by these embodimentscan provide significant benefit to integrated circuits withferroelectric materials. For example, the improved read margin providedby these embodiments enables the manufacture of FRAMs suitable forreliable use in a wider range of applications, such as in systemsintended for elevated temperatures. In addition, these embodimentsimprove the tolerance of the ferroelectric integrated circuits for hightemperature processes such as WCSP packaging, solder reflow and othermounting processes, without necessitating relaxation of the expectedelectrical performance and reliability specifications (e.g., circuitperformance, device sizes, etc.) from what may otherwise be attainablefor applicable technology node. And if instead the ferroelectricintegrated circuits are packaged in conventional molded plasticpackages, the benefits of using polyimide as a stress relief agent areobtained without suffering the degradation in polarizationcharacteristics encountered from conventional cure processing. Inaddition, these embodiments can enable the use of copper metallizationand the resulting increased conductivity in the metal conductorsrelative to aluminum and other materials, despite the high hydrogenconcentration in the silicon nitride barrier layer typically used withcopper, because of the minimal thermal processing involved in curing thepassivation layer as described above.

While one or more embodiments have been described in this specification,it is of course contemplated that modifications of, and alternatives to,these embodiments, such modifications and alternatives capable ofobtaining one or more of the advantages and benefits of this invention,will be apparent to those of ordinary skill in the art having referenceto this specification and its drawings. It is contemplated that suchmodifications and alternatives are within the scope of this invention assubsequently claimed herein.

What is claimed is:
 1. A method of manufacturing an integrated circuit,comprising: forming at least one circuit element comprising a layer of aferroelectric material near a semiconducting surface of a body; thenforming at least one level of conductors overlying the element, eachlevel comprising patterned metal conductors and a dielectric layer;forming a protective overcoat layer over the surface and overlying theat least one circuit element and the at least one level of conductors;then depositing a passivation layer over the protective overcoat layer;and heating the passivation layer to a temperature below a Curietemperature of the ferroelectric material for a duration sufficient tocure the material of the passivation layer into a tensile stress state,and of less than about twenty minutes.
 2. The method of claim 1, whereinthe ferroelectric material is lead-zirconium-titanate.
 3. The method ofclaim 2, wherein the heating step heats the passivation layer to acuring temperature at or below about 390° C.
 4. The method of claim 1,wherein the at least one circuit element comprises a plurality offerroelectric capacitors; and further comprising: before the heatingstep, polarizing the ferroelectric capacitors.
 5. The method of claim 4,wherein the at least one circuit elements further comprise a pluralityof metal-oxide-semiconductor (MOS) transistors, each associated with oneof the ferroelectric capacitors in a plurality of memory cells; whereineach of the plurality of ferroelectric capacitors comprises first andsecond parallel conductive plates disposed on either side of theferroelectric material, the first plate coupled to a plate lineconductor in the integrated circuit and the second plate coupled to asource/drain region of its associated MOS transistor; wherein thepolarizing step comprises: applying a voltage at or above a coercivevoltage across each of the ferroelectric capacitors, at a positivepolarity at the first plate relative to the second plate.
 6. The methodof claim 1, wherein the passivation layer comprises a polymer-containingsoft stress release material having a low elastic modulus as comparedwith SiO₂
 7. The method of claim 6, wherein the polymer-containing softstress release material is selected from the group consisting ofpolyimides, polybenzoxazole (PBO), benzocyclobutene-based polymers(BCB), and fluoro-polymers.
 8. The method of claim 1, wherein thepassivation layer comprises a polyimide; and wherein the heating stepcomprises: exposing the passivation layer to variable frequencymicrowave energy.
 9. The method of claim 1, wherein the heating stepheats the passivation layer from an ambient temperature to a curingtemperature of at least 340° C. and below the Curie temperature of theferroelectric material at a ramp rate of at least 0.40° C. per second.10. The method of claim 1, wherein the heating step maintains thepassivation layer at the curing temperature for a maximum duration ofabout ten minutes.
 11. The method of claim 1, wherein, after theexposing step, the passivation layer cools from the curing temperatureat a ramp rate of at least about 0.40° C. per second.
 12. The method ofclaim 1, wherein the step of forming at least one level of conductorscomprises: depositing a barrier layer comprising silicon nitride; thendepositing a metallization layer comprising copper; and then removingselected portions of the metallization layer to define the conductors.13. An integrated circuit, comprising: at least one circuit elementcomprising a layer of a ferroelectric material, and disposed near asemiconducting surface of a body; at least one layer of insulatingmaterial disposed over the surface and overlying the at least onecircuit element; at least one level of conductors disposed near thesurface; a protective overcoat layer, comprising an insulating material,disposed over the ferroelectric circuit element, the at least one layerof insulating material, and the at least one level of conductors; and apassivation layer overlying the protective overcoat layer, thepassivation layer having a tensile stress state, and formed by a processcomprising: heating the passivation layer to a temperature below a Curietemperature of the ferroelectric material for a duration sufficient tocure the material of the passivation layer into a tensile stress state,and of less than about twenty minutes.
 14. The integrated circuit ofclaim 13, further comprising: a plurality of solder balls near thesurface, in contact with conductors through openings in the passivationlayer.
 15. The integrated circuit of claim 13, wherein the passivationlayer comprises a polymer-containing soft stress release material havinga low elastic modulus as compared with SiO₂
 16. The integrated circuitof claim 15, wherein the polymer-containing soft stress release materialis selected from the group consisting of polyimides, polybenzoxazole(PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers. 17.The integrated circuit of claim 13, wherein the at least one circuitelement comprises a plurality of ferroelectric capacitors, eachcomprising first and second parallel conductive plates disposed oneither side of the ferroelectric material.
 18. The integrated circuit ofclaim 17, wherein the at least one circuit elements further comprise aplurality of metal-oxide-semiconductor (MOS) transistors, eachassociated with one of the ferroelectric capacitors in a plurality ofmemory cells; and wherein each of the plurality of ferroelectriccapacitors comprises first and second parallel conductive platesdisposed on either side of the ferroelectric material, the first platecoupled to a plate line conductor in the integrated circuit and thesecond plate coupled to a source/drain region of its associated MOStransistor.
 19. A method of manufacturing an integrated circuit,comprising: forming at least one circuit element comprising a layer of aferroelectric material near a semiconducting surface of a body; thenforming at least one level of conductors overlying the element, eachlevel comprising patterned metal conductors and a dielectric layer;forming a protective overcoat layer over the surface and overlying theat least one circuit element and the at least one level of conductors;then depositing a passivation layer of a material comprising apolymer-containing film over the protective overcoat layer; and applyingelectromagnetic energy to the passivation layer at a frequencycorresponding to a vibrational frequency of the polymer, to heat thepassivation layer to a temperature below a Curie temperature of theferroelectric material for a duration sufficient to cure the material ofthe passivation layer into a tensile stress state.
 20. The method ofclaim 19, wherein the step of applying electromagnetic energy heats thepassivation layer is performed for a duration of less than about twentyminutes.